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ADF4001,pdf,datasheet

200MHz Clock Generator PLL

软件大小：258KB
更新日期：2009/10/7
软件语言：简体中文
软件类别：机械电子
软件授权：共享软件
软件官网：暂无
适用平台：Vista, Win2003, WinXP, Win2000, NT

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TheADF4001frequencysynthesizercanbeused。

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The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation.

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